1. Technical Field
The present invention relates to a test site for determining the adhesive characteristics of the various materials used in processing a semiconductor chip.
2. Background Art
During the course of the processing of semiconductor chips, a plurality of insulative, metallizing and passivating layers are deposited on the surface of a semiconductor substrate to form the various devices on each chip. These various layers must exhibit some degree of adhesion to one another. If this interlayer adhesion is insufficient, moisture or other impurities can penetrate the seams between layers, causing corrosion or other impurity-induced phenomena which adversely affect the performance of the resulting chip.
Accordingly, various methods have been developed for testing the adhesion between layers used to form a semiconductor device. An article by C. Altman et al ("Measuring Adhesion of Thin Films", IBM Technical Disclosure Bulletin, Vol. 12, No. 10, March 1970, p. 1674) discloses a method of measuring the adhesion between a film and a substrate, in which a testor is bonded to the film and an upward force is imparted thereto to pull the film away from the substrate. A more common testing method (commonly referred to as a "peel test") involves cleaving a film to expose the seam between the film and the substrate and "peeling" the film away from the substrate. In a "90.degree. peel test", the angle between the peeled film and the film remaining on the substrate is approximately 90.degree..
Heretofore, this peel test has been performed on a single layer test structure. For example, a semiconductor wafer having a silicon nitride coating is covered with eight strips of insulative material. By performing a peel test on each strip of the wafer, eight interfaces per wafer can be tested.
It has been found that test wafers constructed in the manner described above are inefficient when used to monitor wafer lot processes. One disadvantage is that only eight interfaces are tested on each test wafer. Another disadvantage is that each test wafer only tests one type of interface; for example, if insulator-metal and insulator-insulator interfaces were to be tested, two different test wafers would have to be produced.